Problem with SoC Encounter 7.1

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1.Soc Encounter 7.1 & search and repair routing after assembleDesign

Dear all,

what is the correct approach of verifying and repairing an assembled
design after partitioning and block level implementation of each partition?
After loading the assembled design (encounter -init dir/top.enc), a
search and repair nanoroute run (iteration 1 to default) results in a
warning (NRDR-175): "External routing was imported and a full chip
verification is not done yet."
How do I perform a full chip verification?
verifyConnectivity + verifyGeometry + verifyProcessAntenna does not seem
to be "full" enough, I get the warning anyway.

I also have another short question: is there something similar to
"nchelp" for SoC Encounter for getting help on error and warning messages?

Thanks for any help,
regards, Mario

2.Problems with soc encounter output to Magic

I had problems when I exported the routing results from soc encounter
to Magic.

In the SoC encounter, after verifying the results, I saved the design
in GDS format, and read it into Magic. But it said that there were
instances as control_VIA0 and control_VIA1, which I think were the
generated vias instances. But I don't have these vias defined in
Magic, so when I read the stream file in Magic, it said that it cannot
find the cell control_VIA0 and control_VIA1.

Meanwhile, in the soc encounter, the wires indeed connected to the
edge of the cell, but when it was imported into Magic, some wires
extended over the edge of the cell, while some did not. I don't know
why it happened.

Thanks in advance!



Renee

3.problem about timing analysis in soc encounter

I have implemented the design on soc encounter 4.2,it can perform the timing
driven wroute and nanoroute smoothly,But when I do timing analysis Using the
embeded timing analysis tool,i found it maybe reported the wrong timing
information,in detail,many latches are involved in the design,so flip-flop
registers and latches mixed together,for instance,a low level latch followed
a rising-edge flip-flop register, and the flip-flop needs capture the output
data from the latch,then the timing delay calculation equation of timing
analysis tool is indicated below:
assumed the clock waveform {0 4},period is 8ns,skew is 0.3ns.
For latch delay:
T(arrival)=T(time given to start)+T(G->Q)+T(combinational delay)
So
T(arrival)=(4ns-0.3ns)+0.2ns+2.2ns=6.1ns
For flip-flop register required time:
T(required timg)=T(rising-edge arrival)-T(latch-enable
time)-T(skew)=8ns-4ns-0.3ns=3.7ns

so the violation time is 3.7ns-6.1ns=-2.4ns

why?? why it calculated like so?? i didnot know indeed.In fact,the time met
my requirement,the slack time is (3.7ns-(6.1ns-3.7ns))=1.3ns
Is it a bug of soc encounter?? pls explain it for me,thanks a lot.

4.Problem with importing verilog netlist into SoC Encounter

Hi,

May I ask for your advice on a problem I am having with loading
verilog netlist into SoC Encounter?

I have a digital design built from schematic entry. The schematic was
built in Virtuoso with XFAB digital cells from D_CELLS library. I
wanted to import this design into SoC Encounter to do the layout,
therefore I used "Virtuoso Verilog Environment for NC_Verilog
Integration" to generate the verilog netlist from the schematic. In
the netlist, the digital cells were connected by position order, such
as

NO2X1 I70 ( nQ, SET, Q);
NO2X1 I71 ( Q, nQ, RESET);

However, this connection is not recognised by Encounter. Once I input
this netlist into Encounter, I got this error message:

**ERROR: (SOCVL-349):    Missing module definition in netlist for
NO2X1.
**ERROR: (SOCVL-209):    [./SR_latch_5V.v:16]: Parser does not handle
connection-by-position for this module.
 at ,.
**ERROR: (SOCVL-349):    Missing module definition in netlist for
NO2X1.
**ERROR: (SOCVL-209):    [./SR_latch_5V.v:16]: Parser does not handle
connection-by-position for this module.
 at ,.
**ERROR: (SOCVL-349):    Missing module definition in netlist for
NO2X1.
**ERROR: (SOCVL-209):    [./SR_latch_5V.v:16]: Parser does not handle
connection-by-position for this module.
 at ).

Only when I changed the connection to connected by port name, the
process started working.

May I ask for your advices on the solution? Is there any method to
generate verilog netlist with ports connected by name? or Should I
modify the setting in Encounter?

Thank you very much!

Dai

5.SoC Encounter via array.

There is a layout to be routed with a constraint on number via 6 in
encounter.
(It could be 6 X 1 or even 2 X 3 which ever is possible)
Is there any option for setting this in the sroute - wroute or nano
route ?

6. diff between silicon ensemble and soc encounter

7. PR warning: cannot find a legal location for instance-soc encounter

8. How to set pins' connection in SOC encounter?