Trivia: Where are you on the HDL Map?

In my travels I have found that -- in the US at least -- HDL choice is 
very strongly correlated to location: designers on the west coast tend 
to use Verilog instead of VHDL, the obverse is the true of folks on the 
east coast.

Designers on each coast like to adopt a cosmopolitan air and claim to be 
_completely agnostic_ about which language that they'd prefer to use -- 
at least during the job interview.  Then when it comes time to actually 
write lines of code, most of them will kick and scream (or at least 
quietly hyperventilate) if they don't get to use the language that 
they're accustomed to.

So -- where are you from, and what HDL do you use?  Have you seen 
patterns of language use in your area change in the last decade or so?

I'm particularly interested in hearing from folks outside the US, and 
from folks in the US but not on the coasts.  Noting whether you're from 
a military hardware background or purely civilian is of interest, too.

TIA.

-- 

Tim Wescott
Wescott Design Services
 http://www.**--****.com/ 

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at  http://www.**--****.com/ 

This has been discussed before, though I can't find the thread. The general pattern is that VHDL/Verilog is about 50/50 in the FPGA world, with a bias towards VHDL on the east side of N. America and Europe. The exception is California where Verilog dominates FPGA work. ASIC work is largely dominated by Verilog.

I'm not sure what the historical reasons for this pattern are. Generally in a given region one tends to be more {*filter*} than the other due mostly to availability of workers and what relevant courses in neighbouring universities have used over the years.

Here in the Toronto area I have the impression it's mostly VHDL, except in the North East where there a fair bit of chip development and Verilog tends to be {*filter*}.

Chris

I'm in Texas and use both VHDL and Verilog because I've worked for
defense and commercial semiconductor companies. The defense sector
generally uses VHDL. Verilog dominates the commercial SoC industry
(which is mostly west coast), though I know of one large development
group at Texas Instruments (Dallas location) that uses VHDL. Sometimes
I'll use both languages in one project because the IP I stitch
together will be a mixture of VHDL and Verilog. In the old days, most
test benches would use VHDL, even if the device itself was done in
Verilog. Now with SystemVerilog and some of the special verification
languages (e.g., Specman), VHDL no longer has the advantage for test-
bench development.

My preferred HDL is Verilog. It's simpler, and I don't like to
remember all of the type conversion semantics that VHDL imposes - just
let me load the register - sheesh!

Darol Klawetter

> I'm particularly interested in hearing from folks outside the US, and from 

Lithuania, Europe. I prefer VHDL. Moving to the new company, which 
specializes in RF, Satellite, etc, so they use VHDL for their production. 

They tought me VHDL in school in NL. I looked at Verilog a few times
but I can't make heads or tails from it. To me Verilog looks like a
netlist from a schematic capture package. I recently did a small CPLD
project. I used VHDL for that as well. I like the way you can do
complex operations with simple functions and use records to keep
related signals together. Using VHDL is more like writing software.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

I'm in the eastern US (New Hampshire) and use pretty much exclusively
Verilog.  I went through college before there were any HDL's, and
spent
the first decade of my career with pencil and vellum for schematics.
My first programmable logic was PALs and I used PALASM for that,
then moved on to Abel, CUPL, and finally back to schematics with
Abel when I started out on FPGA's.  Verilog came later, but it
feels pretty natural to me now.  I use it because it's what makes
me the most productive.  I've never worked for large companies,
so the "existing culture" was never a driving force in tool
selection.  Personally I feel I have benefited by learning logic
design before learning HDL's.  So many of the clueless answer-
seekers on the Xiinx forums seem to think logic design is
some sort of software.  My preference would be to continue
using schematics for a top level design and Verilog underneath.
However, the Xilinx tools have a miserable excuse for a
schematic editor since they dropped Aldec and rolled their
own.  It seems Xilinx isn't very interested in schematics and
so those of us who can't afford expensive third party tools
learn to live without it.

Grumble...
-- Gabor

Seattle, which is on the coast but is mostly a VHDL town, unlike Oregon 
and California. I use both VHDL and Verilog. I slightly prefer VHDL, 
however many of the reasons to prefer one language over the other have 
gone away...Except for the impact of SystemVerilog, which I have not yet 
used. Civilian projects.


-- 
Phil Hays
Phil underbar Hays at ieee dot org

I started FPGA design using schematics in the 4000 series Xilinx
parts.  I had a new job where they sent me to school to learn their
new design package where they had one day on their HDL tool in VHDL.
I came back and told the management that we should not design in
schematic anymore and we switched.  Although it was a government
contracting position, I don't think they influenced the choice of
language.

Later I worked for a comms test equipment company and they only used
Verilog, so I worked in that without any training.  When I left there
Verilog didn't stick with me and I've been using VHDL since... until
the last month when I had a task where the customer wanted Verilog.
So I spent the time to actually learn the language, a bit at least.  I
found Verilog pretty useful and didn't have the hangover I usually get
from strong typing.  I did find one bug relating to my assumption on
what happens when a counter is decremented below 0 (I assumed -1 would
be next and Verilog assumed it should wrap around or something).  I
can't say I wasn't warned...

So I may spend more time with Verilog.  I learned quite a few things
about Verilog doing this project and even talked about some that I
found to be uniquely useful only to find that with the 2008 redo of
VHDL it has them too for the most part.

So the only real difference, if I understand it correctly, is that
while Verilog lets you do what you want without excessive explanation,
it also makes assumptions about what you mean which may give you
something different than what you intended.  Otherwise I think Verilog
is just plain easier to work with. Just learn the Verilog assumptions
and you should be pretty good to go.

Rick

I'm in the UK (South West Scotland) and use VHDL. Like one of the other 
posters I much prefer to use schematic entry at the top level. I have an 
Aldec license so I use their schematic entry and it does all that tedious 
gluing of the VHDL blocks together. I write the blocks in VHDL but use the 
Aldec tools to generate template files.

I would look at Verilog but my Aldec license would need an expensive upgrade 
so there would need to be a compelling commercial reason to go that way.

Michael Kellett 

Tim Wescott < XXXX@XXXXX.COM > writes:


Summary: UK-based, VHDL, automotive applications.  

We were "shown" VHDL at University, we built a stepper-motor
controller in Abel.  I was taught VHDL at work within a year or so of
graduation (some of my colleagues at that time were using AHDL and
schematic entry) and did some small tasks.

I've been using VHDL seriously since 2000.  I don't miss schematics, I
use Emacs to do the tedious wiring part of the top-level design and
Visio to document the block interactions.

In the last couple of years I'm starting to feel some
"push-out-of-VHDL" because the simulation vendors have been pushing
SystemVerilog so much.  An awful lot of verification now seems to be
being done in SV, even of VHDL RTL code. 

I'm currently VHDL throughout, but wondering if I should change :0

Cheers,
Martin

-- 
 XXXX@XXXXX.COM  
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
 http://www.**--****.com/ 

Wow, strange that you have the same opinion as me, except the
languages are reversed!
I use Verilog almost exclusively (have had to hack some VHDL to add
ports from time to time, for debug of IP cores provided to me)
Whenever I look into a VHDL design, I always marvel at how needlessly
verbose it is with the package and entity, etc. How hard it is to find
the 'meat' of the code, how crazy the case insensitivity is, and how I
have to convert signals to and from std_logic_vector to other types to
simply increment a value. (I know the strict typing is part of VHDL's
pros for most people - but it's not for me)

I suppose it's what you are used to - if you use Verilog, anything
else will look alien, and likewise for VHDL.

As for the Map - work in an ASIC house, in northern europe, and the
company is San Jose based. We use verilog exclusively for ASIC design,
but IP we ship externally is in VHDL

I'm on the west coast, and use VHDL (although my last gig
involved Verilog).


Likewise.


Started with 82S153s and 82S105s, where I had to mark up
the map and send it off to Signetics for programming.
When we got a programmer, but I had to use freeze spray
while the parts were programming.

 I'd forgotten CUPL -- what a great language (compared
with PALASM or even Abel). I used to work across the
street from the guy who wrote it, so I would just
walk across the road for tech support.


Likewise.
I use Aldec for VHDL sim. I couldn't get them to cut me
a deal on Verilog, so I ended up using the free Altera ModelSim.
If I get more Verilog gigs I'll probably spring for Aldec. 

Started my career in CO.  Started with Verilog but also used VHDL (company
PQR vs XYZ).  I am fluent with Verilog and VHDL but have a slight
preference for Verilog, simply because it is the language I first used and
it's little ingrained.

I am now in MN, my current and previous projects are in Verilog.

I would also state that I use MyHDL as frequently as possible for IP blocks
if the boss(es) allow.

I would like to think I would be agnostic to HDL language selection on a
particular project.  I might be more opinionated on tools.

Chris Felton	   
					
---------------------------------------		
Posted through  http://www.**--****.com/ 

<snip>

The following is a list of projects I have worked on over the last 10
years.  This includes time in CO and MN (since this post is interested in
geo-local).  

The duration (in months) includes time actively modifying the HDL,
implementation, debug, fixes, feature adds.  Duration does *not* include,
design and documentation.  In this context I define a project as an
opportunity to use a different HDL.

Duration   HDL        Target Tech
----------------------------------
9          Verilog      FPGA
6          Verilog      FPGA
6          Verilog      ASIC
2          Verilog/SV   FPGA
3          Verilog      ASIC
6          VHDL         FPGA
3          VHDL         FPGA
5          VHDL         FPGA
3          Verilog      FPGA
3          MyHDL        FPGA
3          Verilog      FPGA
3          Verilog      ASIC

Chris Felton	   
					
---------------------------------------		
Posted through  http://www.**--****.com/