Hello, Is there any way to know in a Makefile which target is wanted to build? E.g. if I have targets all, A and B, how can I use conditionals in the Makefile depening on the target? Thank you, Zuheyr
Hello, Is there any way to know in a Makefile which target is wanted to build? E.g. if I have targets all, A and B, how can I use conditionals in the Makefile depening on the target? Thank you, Zuheyr
The MAKECMDGOALS variable is automatically set to the list of goals (i.e. targets) you specified on the command line. So you can do something like ifeq($MAKECMDGOALS,all) do something endif Take care, it seems to be GNU make specific. Regards, Jens -- \ Jens Thoms Toerring ___ XXXX@XXXXX.COM \__________________________ http://www.**--****.com/
1.GNU Makefile with phony target and source files as dependencies of a target
Hello guys, I have a question about GNU make running on the Solaris 8 platform. We have a GNU Makefile which has a "depend" target (for the usual concept of make depend in C++ programming) which looks like this: depend : prep $(patsubst %.cc,%.o , $(OBJ)) $(CC) $(CPPFLAGS) -xM1 $? > .depend Obviously this has a problem, in that the prep target (along with the depend target) is phony, and so the CC command to generate dependencies fails with the "prep" value passed as a filename in "$?" in the command. I had an idea to change the compilation command to: $(CC) $(CPPFLAGS) -xM1 $(filter %.cc,$?) > .depend and I believe this should work. My question is: while this solution might work, I'm not sure it is the "preferred" solutoin using GNU make. Is this a "good enough" solution? Or this there another, "preferred" solution that is better? If there is, please let me know what it might be. Thanks
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