procedure inside package body and modelsim error

by **Olaf Petzold** » Fri, 13 Apr 2007 04:14:58 GMT

Hi,

I try to move out some stuff for use with testbenches. Anyway, I wote:

---8<---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package tb_pkg is
   procedure tic(clk : in time);
end package tb_pkg;


package body tb_pkg is
   procedure tic(clk: in time) is
   begin
      wait until rising_edge(clk); -- line73
   end procedure;
end package body tb_pkg;
--->8--

modelsim got:
# ** Error: ../source/vhdl/tb_pkg.vhd(73): No feasible entries for
subprogram "rising_edge".
# ** Warning: [2] ../source/vhdl/tb_pkg.vhd(73): Wait statement has no
sensitivity list or time out clause.

Mmhh, this happens only by use with the package. How to get it working
and what is the reason for? It's inspired by
 http://www.**--****.com/ ~mike_treseler/test_uart.vhd ;-)

Thanks
Olaf

by **Jonathan Bromley** » Fri, 13 Apr 2007 06:45:11 GMT




I suspect your "clk" should be of type "std_logic", not "time".


Now I'm sure!  TWO things wrong here:

(1) there's no rising_edge function for "time", unless you
wrote it yourself.  Let's assume that you meant "std_logic".

(2) rising_edge needs a *signal* to work on, because
it needs to test the signal's 'event attribute.  You are
giving it a *constant*, the procedure's input parameter.

Let's try again... with a tick-count parameter for
added versatility...

package tb_pkg is
  procedure tic(signal clk: in std_logic; N: in positive := 1);
end package;
package body tb_pkg is
  procedure tic(signal clk: in std_logic; N: in positive := 1) is
  begin
    for i in 1 to N loop wait until rising_edge(clk); end loop;
  end;
end package;

Should be OK now :-)

Presumably it worked when you had the procedure in a process,
because you didn't pass "clk" as a parameter, but used it directly?
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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The contents of this message may contain personal views which 
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by **Mike Treseler** » Fri, 13 Apr 2007 06:50:12 GMT




Add the clock to your sim package like this:

     signal clk_s : std_ulogic := '0'; --
     procedure tic;                    --
       wait until rising_edge(clk_s);  --

Also see the "Remote Testbench Procedure"

       -- Mike Treseler

by **Andy Peters** » Fri, 13 Apr 2007 07:25:17 GMT



You need to put another set of library/use clauses before the package
body declaration.

-a

by **kennheinrich** » Fri, 13 Apr 2007 07:31:49 GMT





Olaf,

One problem is that 'time' doesn't have rising edges (as meant by the
rising_edge function: a change which brings the signal to a value of
'1'). Time is just an integer range. Logic signals have rising
edges.   I suspect that you either want to define clk as std_logic, or
(for simulation) change your procedure to wait until time >
some_next_value_of_time.

 - Kenn

procedure inside package body and modelsim error

procedure inside package body and modelsim error

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