NC-Verilog hdl.var problem?

Similar Threads:

1.How to include paths to Header Files in NC-Sim/NC-Verilog

Can someone show me how to include header file paths in the PC based NC-Sim
environment ?? In unix I would have just done +include+<directory_name>+ in
my run.f file;
I tried adding the paths in the  "include" window in the verilog compiler
option but it still complains that it cant find "sys_defs.vh" that I have in
a number of my source files as -
`include "sys_defs.h"
Thanks for your help,

Rajat

2.verilog HDL problem

what is the error in the following code. in it the main module is
"test". in that module's "always" block another module "counter" is
called. but it shows error. how can i solve the problem? how can i
call another module in always block?


module counter(clock, reset, count);
    input clock, reset;
    output [3:0] count;

    reg [3:0] next_count,count;

    always@*
    begin
        if(count<15)
            next_count=count+4'd1;
        else
            next_count=count;
    end

    always@(posedge clock)
    begin
        if(reset)
           count<=4'd0;
        else
           count<=next_count;
    end
endmodule


module test(clock,reset,count);
input clock, reset;
output [3:0] count;
reg [3:0] count;
always @(clock)
    counter(clock, reset, count);
endmodule

3.What's the difference between HDL Compiler(Presto Verilog) & HDL Compiler for Verilog?

In article < XXXX@XXXXX.COM >, 
 XXXX@XXXXX.COM  says...
> Hi,
>     I'm reading the Synopsys documentations. There are two documents.
> One is HDL Compiler for Verilog Reference Manual, the other is HDL
> Compiler (Presto Verilog) Reference Manual. Can somebody tell me
> what's the difference between them?
> Best wishes,
> Peng
 
Synopsys' old verilog reader / synthesizer is the HDL compiler.  Presto 
is their newer (more supported) verilog reader / synthesizer.  The main 
difference between the two is that they have different bugs.

-- 
Rich Iachetta
I do not speak for IBM

4.Compilation order of verilog files in NCVerilog/VCS simulator to choose the dealy mode

Hi..

Recently, I started learning to do timing simulation using NCVerilog
and VCS simulator. I have the following problem of specifying the
correct delay mode compiler directive..

In the testbench, I specified `delay_mode_distributed and
in the DUT (design under test) I specified `delay_mode_path (The sdf
file is called using $sdf_annotate in DUT)...

With this set up , my understanding is that, the testbench should
execute under distributed delay;
and the DUT should execute under path delay;

If that is true, then I have the following strange observation:

During compilation of verilog file, If I first compile testbench; and
then compile DUT....Then there is no problem..The testbench is executed
with distributed delay; and DUT with path delay...

But, if we compile, DUT first; and then Testbench...In this case, the
DUT is also executed under distributed mode instead of path mode...This
is kind of wierd...

If anyone of you know the solution for this..please do let me know..It
will be of great help...

Please, let me know if I need to provide any other information..

Thanks,
Kesav..

5.config-endconfig in NC-Verilog

I'm trying to use a configuration (config endconfig construct)
with NC-Verilog. The goal is to have multiple configurations
available in one library. Each configuration would bind a different
implementation to the DUT (RTL, post-synthesis netlist, post place
and route netlist).

In order to test the principle, I created a small example with a
top module instantiating a leaf module. This leaf module is bound
to a module from different libraries. So I have two configurations:

File top_cfg1.v:
config top_cfg1;
   design work.top;
   default liblist work;
   cell leaf use lib1.leaf;
endconfig

File top_cfg2.v:
config top_cfg2;
   design work.top;
   default liblist work;
   cell leaf use lib2.leaf;
endconfig

In ModelSim, this works like a charm.

In NC-Verilog, trying to compile a configuration gives:

$ ncvlog verilog/top_cfg1.v
ncvlog: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
config top_cfg1;
      |
ncvlog: *E,EXPMPA (verilog/top_cfg1.v,1|5): expecting the keyword 
'module', 'macromodule' or 'primitive'[A.1].

It would seem that the new Verilog-2001 keywords are turned off with the 
-v1995 switch, but that is not the case.

Does this version of ncvlog lack support of configurations? What is the 
latest version of NCSIM anyway? (I cannot find that on the Cadence WEB 
site)

Thanks.
Paul.

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