NC-Verilog hdl.var problem?



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NC-Verilog hdl.var problem?

Postby Davy » Mon, 13 Feb 2006 19:04:31 GMT

Hi all,

I am a NC-Verilog newbie and confused with NC-Verilog's file.

In cds.lib, map logical lib name to physical location
DEFINE ic_lib /lsi_lib

Why map again in hdl.var?
DEFINE LIB_MAP (myfile.v => mylib, ./cell_lib => techlib, + => worklib)

Does "myfile.v => mylib" means compile myfile.v to mylib?
And what's "+ => worklib" mean in LIB_MAP?

Best regards,

Re: NC-Verilog hdl.var problem?

Postby Ajeetha » Mon, 13 Feb 2006 21:33:20 GMT

>> In cds.lib, map logical lib name to physical location

hdl.var --> Defines HDL Variables such as:

      Files to library maps

Read that from a VHDL perspective - one can have several libraries and
have different design units compiled to different libraries. For that
you need a mechanism to associate which files go to which library.

This specifies a default WORK for you. Again little VHDL centric - VHDL
needs a WORK to compile any thing. One can override this with command
line -work option. Note that the "worklib" above is a LOGICAL name and
that must be defined by a cds.lib to a physical directory.

Slowly becoming a NC expert you are :-)

Any other file goes there - i..e like "*" in regular expressions,
default in a Verilog case statement etc.

Ajeetha, CVC

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