## From VHDL to gates and LUTs (newbie)

vhdl

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• 1. declaring real numbers (2^15-1) and (-2^15) in vhdl
hi i would like to know how to declare the numbers in vhdl.the numbers are (2^15-1) and (-2^15). when i declare it using the REAL modelsim returns a error saying it is out of range.how to overcome it thanks hari
• 2. mixing sampled sine waves
Hi, I have a question regarding mixing discrete sine waves. If you have two sine waves sin(w1*t) and sin(w2*t) and they are sampled at the same rate. If you are mixing them in a receiver operation, we are supposed to get at the output of the mixer the sum and difference of frequencies. But it is just the values that we are multiplying isn't it, at the sampled time instants? How do we end up getting a difference frequencies and sum frequencies which have to be low pass filtered? If I implemented this in VHDL and used math_real library functions sin() and real variables, I would just be multiplying the two numbers at each time sample. This value would encompass the frequency of the sine wave. However I donot understand how I would be getting a difference in frequency and sum in frequency terms? I have read from trigonometry and analog communications but somehow I am missing some essence here. Could you please let me know how the above is possible? I would greatly appreciate a response. Thanks, Viswanath
• 3. Counting bits
I am trying to implement a simple circuit that counts the number of 1's in a 16 or 32 bit register. I am fairly new to VHDL and have implemented it the following way for i in 15 downto 0 loop if (Reg(i) = '1') then Bitcount := BitCount + 1; end if; end loop; in synthesizing this code, i found that this generated numerous 16 bit adders. is there a better way to implement consider the solution can be stored in only 4 bits? Steve

### From VHDL to gates and LUTs (newbie)

```Hello NG!

I'm learning VHDL, but still have to understand how my VHDL-code will
end up as gates and LUTs etc in a FPGA...

I did search google, but all I found was some complex sites describing
how it worked, so I try this NG. Good links which describes the above
for a newbie are highly appreciated! :o)

1) Default-values?
I have a signal in my architecture of a entity, which I give a default
value, like this:
signal counter : std_logic_vector(7 downto 0) := (others => '0');

Will this default value be put in the FPGA as well? Or should I code
my architecture as if it could be undefined as default?
Maybe it differ from FPGA to FPGA? I'm using a FPGA from the Spartan
family.

2) What's happening when I synthesize?
Can someone in simple steps describe what is happening when I
synthesize, implement design, generate programming file etc. from my
VHDL-code? That could be cool! (I'm using a free version of Xilinx
ISE, but I guess the terms are general).

3) UCF-files
User Constraints Files are mainly (at least for a beginner like me)
how my pins of my FPGA are connected to the outer world, right? - and
how I attach them to inputs on my entities in my VHDL-code.

4) How is my FPGA "booted"?
Now everything has been put in the FPGA and I power up FPGA. Will it
for some time, before my entities starts working as expected? I guess
it takes some times to initialize the FPGA? I guess you will refer me
to the datasheets of the specific FPGA on this... ;o) I want to know
issue. :o)

--
SanSaurus

```

### Re: From VHDL to gates and LUTs (newbie)

```

Usually not.

Use a reset input and code specific reset assigments.

A netlist is generated that simulates the

All pins will be 'Z' until the image file is loaded.
Next the reset pulse is applied, and outputs will
start working the same as the functional simulation.

-- Mike Treseler
```

### Re: From VHDL to gates and LUTs (newbie)

```

Some synthesizers can provide a schematic view (gates, flipflops, muxs etc)
of what they have produced.

Jeroen

```

```Hi Group,
I am not sure if this is the right group to post this
query,but I am doing it anyway.I am relatively new to VHDL and am tring
to understand why
VHDL gate level descriptions simulate slower than verilog models.I was
told that it was because how the VHDL model gets evaluated (delay
models) that makes it slower.I didnt quite follow this and if somebody
in the group could point me towards a more detailed explanation ,it
would be great.I would also like to know why do we see better VHDL
performace at behavioural descriptions(as compared to verilog
behavioural descriptions.).I am sorry if this has been discussed
previously.

Thanks,
Abilash.

```