xilinx xst - dont change part type ( n gate delay)



  • 1. i need solutions of chapter 5 wireless communication by Andrea Goldsmith
    i need solutions of chapter 5 wireless communication by Andrea Goldsmith.. plz if any one can help me in this regard... reply here or to my mail address
  • 2. DCM Core cannot generate output
    Hello All, I have instantiated a DCM core with an input frequency of 32 MHz clock signal from the device. I would like to recieve a 96 MHz output signal from the DCM core, so I set the .xwa file to multiply the incomming signal by 3. When I generate the bit stream and run the design on my board, the FX pin doesn't seem to produce a frequency. I know I am doing something incorrectly here, do I have to reset the DCM core, or use another signal from the DCM core to obtain my desired output or whatever ... please help. Thanks,

xilinx xst - dont change part type (re: n gate delay)

Postby colin » Sat, 01 Sep 2007 03:37:03 GMT

 My n gate delay is actualy working now,
well at least in the simulation
thanks to those who tried to help :)

However I found the problem after reading through the xst manual a few 
well actually that didnt help in itself but its always worth refreshing -
can only take in a certain amount each read,
but I found the NOREDUCE attribute,
wich does exactly what I wanted
ie allows extra (guard) logic to be put in to acount for race conditions 
glitches etc
without it being removed.

however its only available for coolruner,
so I changed to coolruner and it worked :D

I also tested the other attributes SAVE NET and KEEP
any 1 of the 3 atributes makes it work too,

so I changed back to spartan3 to see what hapened
and that worked too,
however I realised that when I changed the code the simulator didnt
reflect the changes,
also the gates had been optimized out in the post map floorplanner.

so I created a new project with few gates in a spartan 3 and the save net 
and keep attributes worked properly,
changed to coolrunner then back to spartan and it didnt work.

so changing the ISE to coolrunner is a one way ticket.

it would be nice to fit it in a coolruner but it quickly outgrew this,
I am expecting to get a spartan 3 board to do the development
but theres a chance can trim it down to a coolrunner.

anyway thought id share this.

I can now get a 0.7ns increment by changing the number of gates,
this all seems to be implemented with LUTs, Im looking to see if other ways 
will add a slightly different amount.

ofc i can always adjust the wire length via placement.

to test it im using a small ring oscillator:-

a(0)<=not (a(2) and  a(3) and enable);
if a(0) ='1' or fast ='1' then
end if;
--a(1)<=a(0) or fast;
a(2)<=a(0) and a(1);
a(3)<=a(2) or fast;


Colin =^.^= 

Similar Threads:

1.set dont touch attribute in xilinx xst?

   Is there a "set_dont_touch" equaivalent version of Xilinx Xst
attribute. Or is it only in synopsys?

2.Xilinx error xst: 1706 & 1847

How to solve error 1706 & 1847 occur during synthesis of design and
give following messege:
PL$_7>: port <_n2472> of logic node <_n0923> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2468> of logic node
<_n0918> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2466> of logic node
<_n0917> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2466> of logic node
<_n0916> has no source
ERROR:Xst:1847 - Design checking failed
ERROR: XST failed

3.Xilinx XST 9.1 and casez statement?

Through a lot of bumbling in Webpack 9.1i.03, I found that my 
state-machi\nes don't synthesize properly if I use the casez statement:

module x(
  input wire [1:0] ps,
  output reg [1:0] ns

localparam [2:0] STATE_1 = 3'd0,
   STATE_2 = 3'd1,
  STATE_3 = 3'd2,
  STATE_4 = 3'd3;

always @* begin : state_machine
case ( ps )
  STATE_1: ns = STATE_2;
  STATE_2: ns = STATE_3;
  STATE_3: ns = STATE_4;
  STATE_4: ns = STATE_1;
  'hz : ns = STATE_1;   // <-  all other values default to here
  default : ns = 'hX;  // <- Simulation-only, trap 'X's on ps[2:0]
endcase // ps


XST completely optimizes out my logic!
"Slice Usage: 0" ?!?!

(For those wondering, 'casez' is a coding-trick to get Verilog-simulations 
 propagate 'X's through the state-machine.  For synthesis, the 'hZ forces
 all unused encodings/values to default to the known 'STATE_1', instead of 
just leaving up to the tool to randomly optimize it.)

Now, I can switch back to using a traditional case() statement, but then I 
sacrifice the simulation-X behavior.

Anybody else see this behavior with casez? Is it time to file a bug-report? 

4.XST bug - Xilinx says it's solved in 7.1

This has been acknnowledged by Xilinx tech support as a bug which
they said got fixed in version 7.1. (I didn't double-check).

Bert Cuzeau

5.Xilinx XST Error

At the bottom of this post is the code.

First, let me say that I have run this "program" through a TBW, and it
seems to simulate correctly.

Second, I'll describe what this module does (or at least, should do).
8 bytes (along with 5 address bits that are carried).  When 8 bytes
come in, it outputs all 8 at once in a 64 bit value (again, along with
the carried 5 bit address).

The latch line is mostly simply passed through, except that it is
additionally used to reset the buffer pointer.

Am I making this task overly complex?  If not, what's going on with it?

When I run the "implement design" task, I get the following warnings /

*                            HDL Analysis
Analyzing Entity <queue> (Architecture <behavioral>).
WARNING:Xst:790 - "C:/xilinx/tutorial/queue.vhd" line 46: Index
value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <data_buffer> may be accessed with an
index that exceeds the array size. This could cause simulation
ERROR:Xst:827 - "C:/xilinx/tutorial/queue.vhd" line 23: Signal
DATA_OUT<57> cannot be synthesized, bad synchronous description.

I'm indeed new to VHDL, and I'm just not clear on what the problem is
here.  Any help would be greatly, greatly appreciated.  I can supply a
zip of the project to anyone interested in helping enough for that.


Alex McHale

library IEEE;

entity queue is
    Port ( DATA_IN : in  STD_LOGIC_VECTOR (7 downto 0);
           LATCH_IN : in  STD_LOGIC;
           CLOCK_IN : in  STD_LOGIC;
			  ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0);
           DATA_OUT : out  STD_LOGIC_VECTOR (63 downto 0);
           LATCH_OUT : out  STD_LOGIC;
           CLOCK_OUT : out  STD_LOGIC;
			  ADDRESS_OUT : out STD_LOGIC_VECTOR (4 downto 0));
end queue;

architecture Behavioral of queue is
	type ram_type is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0);
	signal data_buffer : ram_type := ("00000000", "00000000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000");
	signal buffer_write_offset : STD_LOGIC_VECTOR (3 downto 0) := "0000";
	signal address_buffer : STD_LOGIC_VECTOR (4 downto 0) := "00000";
	process (CLOCK_IN, LATCH_IN)
		if rising_edge( LATCH_IN ) then
			buffer_write_offset <= "0000";
			LATCH_OUT <= '1';
		elsif falling_edge( LATCH_IN ) then
			LATCH_OUT <= '0';
		elsif rising_edge( CLOCK_IN ) then
			CLOCK_OUT <= '0';

			if buffer_write_offset = "0000" then
				DATA_OUT( 7 downto 0 ) <= data_buffer( 0 );
				DATA_OUT( 15 downto 8 ) <= data_buffer( 1 );
				DATA_OUT( 23 downto 16 ) <= data_buffer( 2 );
				DATA_OUT( 31 downto 24 ) <= data_buffer( 3 );
				DATA_OUT( 39 downto 32 ) <= data_buffer( 4 );
				DATA_OUT( 47 downto 40 ) <= data_buffer( 5 );
				DATA_OUT( 55 downto 48 ) <= data_buffer( 6 );
				DATA_OUT( 63 downto 56 ) <= data_buffer( 7 );
				ADDRESS_OUT <= address_buffer;
				CLOCK_OUT <= '1' after 1ns;
			end if;

			data_buffer( conv_integer( buffer_write_offset ) ) <= DATA_IN after
			address_buffer <= ADDRESS_IN after 5ns;
			buffer_write_offset <= (buffer_write_offset + 1) and "0111" after
		end if;
	end process;
end Behavioral;

6. VHDL-200X-FT Packages and Xilinx XST Error

7. n gate delay

8. matched delays in Xilinx ISE?

Return to vhdl


Who is online

Users browsing this forum: No registered users and 21 guest