xilinx xst - dont change part type ( n gate delay)

Similar Threads:

1.set dont touch attribute in xilinx xst?

   Is there a "set_dont_touch" equaivalent version of Xilinx Xst
attribute. Or is it only in synopsys?

2.Xilinx error xst: 1706 & 1847

How to solve error 1706 & 1847 occur during synthesis of design and
give following messege:
PL$_7>: port <_n2472> of logic node <_n0923> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2468> of logic node
<_n0918> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2466> of logic node
<_n0917> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2466> of logic node
<_n0916> has no source
ERROR:Xst:1847 - Design checking failed
ERROR: XST failed

3.Xilinx XST 9.1 and casez statement?

Through a lot of bumbling in Webpack 9.1i.03, I found that my 
state-machi\nes don't synthesize properly if I use the casez statement:

module x(
  input wire [1:0] ps,
  output reg [1:0] ns
  );

localparam [2:0] STATE_1 = 3'd0,
   STATE_2 = 3'd1,
  STATE_3 = 3'd2,
  STATE_4 = 3'd3;

always @* begin : state_machine
case ( ps )
  STATE_1: ns = STATE_2;
  STATE_2: ns = STATE_3;
  STATE_3: ns = STATE_4;
  STATE_4: ns = STATE_1;
  'hz : ns = STATE_1;   // <-  all other values default to here
  default : ns = 'hX;  // <- Simulation-only, trap 'X's on ps[2:0]
endcase // ps
end

endmodule

XST completely optimizes out my logic!
"Slice Usage: 0" ?!?!

(For those wondering, 'casez' is a coding-trick to get Verilog-simulations 
to
 propagate 'X's through the state-machine.  For synthesis, the 'hZ forces
 all unused encodings/values to default to the known 'STATE_1', instead of 
just leaving up to the tool to randomly optimize it.)

Now, I can switch back to using a traditional case() statement, but then I 
sacrifice the simulation-X behavior.

Anybody else see this behavior with casez? Is it time to file a bug-report? 

4.XST bug - Xilinx says it's solved in 7.1

This has been acknnowledged by Xilinx tech support as a bug which
they said got fixed in version 7.1. (I didn't double-check).

Bert Cuzeau

5.Xilinx XST Error

At the bottom of this post is the code.

First, let me say that I have run this "program" through a TBW, and it
seems to simulate correctly.

Second, I'll describe what this module does (or at least, should do).
8 bytes (along with 5 address bits that are carried).  When 8 bytes
come in, it outputs all 8 at once in a 64 bit value (again, along with
the carried 5 bit address).

The latch line is mostly simply passed through, except that it is
additionally used to reset the buffer pointer.

Am I making this task overly complex?  If not, what's going on with it?

When I run the "implement design" task, I get the following warnings /
errors:



=========================================================================
*                            HDL Analysis
*
=========================================================================
Analyzing Entity <queue> (Architecture <behavioral>).
WARNING:Xst:790 - "C:/xilinx/tutorial/queue.vhd" line 46: Index
value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <data_buffer> may be accessed with an
index that exceeds the array size. This could cause simulation
mismatch.
ERROR:Xst:827 - "C:/xilinx/tutorial/queue.vhd" line 23: Signal
DATA_OUT<57> cannot be synthesized, bad synchronous description.




I'm indeed new to VHDL, and I'm just not clear on what the problem is
here.  Any help would be greatly, greatly appreciated.  I can supply a
zip of the project to anyone interested in helping enough for that.

Thanks!

Alex McHale








library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity queue is
    Port ( DATA_IN : in  STD_LOGIC_VECTOR (7 downto 0);
           LATCH_IN : in  STD_LOGIC;
           CLOCK_IN : in  STD_LOGIC;
			  ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0);
           DATA_OUT : out  STD_LOGIC_VECTOR (63 downto 0);
           LATCH_OUT : out  STD_LOGIC;
           CLOCK_OUT : out  STD_LOGIC;
			  ADDRESS_OUT : out STD_LOGIC_VECTOR (4 downto 0));
end queue;

architecture Behavioral of queue is
	type ram_type is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0);
	signal data_buffer : ram_type := ("00000000", "00000000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000");
	signal buffer_write_offset : STD_LOGIC_VECTOR (3 downto 0) := "0000";
	signal address_buffer : STD_LOGIC_VECTOR (4 downto 0) := "00000";
begin
	process (CLOCK_IN, LATCH_IN)
	begin
		if rising_edge( LATCH_IN ) then
			buffer_write_offset <= "0000";
			LATCH_OUT <= '1';
		elsif falling_edge( LATCH_IN ) then
			LATCH_OUT <= '0';
		elsif rising_edge( CLOCK_IN ) then
			CLOCK_OUT <= '0';

			if buffer_write_offset = "0000" then
				DATA_OUT( 7 downto 0 ) <= data_buffer( 0 );
				DATA_OUT( 15 downto 8 ) <= data_buffer( 1 );
				DATA_OUT( 23 downto 16 ) <= data_buffer( 2 );
				DATA_OUT( 31 downto 24 ) <= data_buffer( 3 );
				DATA_OUT( 39 downto 32 ) <= data_buffer( 4 );
				DATA_OUT( 47 downto 40 ) <= data_buffer( 5 );
				DATA_OUT( 55 downto 48 ) <= data_buffer( 6 );
				DATA_OUT( 63 downto 56 ) <= data_buffer( 7 );
				ADDRESS_OUT <= address_buffer;
				CLOCK_OUT <= '1' after 1ns;
			end if;

			data_buffer( conv_integer( buffer_write_offset ) ) <= DATA_IN after
5ns;
			address_buffer <= ADDRESS_IN after 5ns;
			buffer_write_offset <= (buffer_write_offset + 1) and "0111" after
10ns;
		end if;
	end process;
end Behavioral;

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7. n gate delay

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