Xilinx FIFO CoreGen: Datacount goes to zero upon full flag

Similar Threads:

1.Xilinx Coregen - FIFO

2.How to determine number of block rams in a Coregen Fifo

Guys.
This must seem quite trivial, but how can I tell how many block rams I
am using in a xilinx coregen'ed fifo. Example, how many block rams are
being used in a 256bit by 32 deep fifo.

thanks

3.Xilinx Coregen (FFT): Unconected output pin/no driver

Hi,

I try to use the FFT core produced by Xilinx Corgen (module name: 
fft_64). In simulation everything seems to be alright, but if I try 
to create a bit file (xst->ngdbuild->map->par->bitgen), I get the 
following:

WARNING:NgdBuild:440 - FF primitive 'FFT/blk00000111' has 
unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'FFT/blk00000114' has 
unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'FFT/blk00000166' has 
unconnected output pin
[...]
WARNING:NgdBuild:452 - logical net 'FFT/blk00000003/sig000029c1' has 
no driver
WARNING:NgdBuild:452 - logical net 'FFT/blk00000003/sig000029c2' has 
no driver
[...]
bitgen -w test_fft
[...]
ERROR:PhysDesignRules:10 - The network <FFT/blk00000003/sig000029c2> 
is completely unrouted.
ERROR:PhysDesignRules:10 - The network <FFT/blk00000003/sig000029c1> 
is completely unrouted.

After that, the compilation stops. If I search for e.g. 
blk00000003_sig000029c1 in fft_64.vhd I find it only connected to 
the input of a LUT, to nothing else.

My code is attached, I'm using the Xilinx tools from the command line.

Do you have any hints?

Regards,

  Norbert



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity test_fft is
   generic(
     adder_width           : positive := 24;
     adder_depth           : positive := 2;
     adc_data_width        : positive := 12;
     window_ram_adr_width  : positive := 8;
     window_ram_data_width : positive := 12;
     wola_num_blocks       : positive := 4
     );
   port (
     CLK, RST   : in  std_logic;
     FFT_XK_RE : out std_logic_vector(30 downto 0);
     FFT_XK_IM : out std_logic_vector(30 downto 0);
     ADC_DATA: in std_logic_vector(23 downto 0)
     );
end test_fft;


architecture Behavioral of test_fft is
component fft_64
         port (
         xn_re: IN std_logic_VECTOR(23 downto 0);
         xn_im: IN std_logic_VECTOR(23 downto 0);
         start: IN std_logic;
         nfft: IN std_logic_VECTOR(4 downto 0);
         nfft_we: IN std_logic;
         fwd_inv: IN std_logic;
         fwd_inv_we: IN std_logic;
         sclr: IN std_logic;
         ce: IN std_logic;
         clk: IN std_logic;
         xk_re: OUT std_logic_VECTOR(30 downto 0);
         xk_im: OUT std_logic_VECTOR(30 downto 0);
         xn_index: OUT std_logic_VECTOR(5 downto 0);
         xk_index: OUT std_logic_VECTOR(5 downto 0);
         rfd: OUT std_logic;
         busy: OUT std_logic;
         dv: OUT std_logic;
         edone: OUT std_logic;
         done: OUT std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of fft_64: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fft_64: component is true;


begin
  FFT: fft_64
                 port map (
                         xn_re => ADC_DATA,
                         xn_im => ADC_DATA,
                         start => '1',
                         nfft => "00110",
                         nfft_we => '0',
                         fwd_inv => '0',
                         fwd_inv_we => '0',
                         sclr => '0',
                         ce => '1',
                         clk => CLK,
                         xk_re => FFT_XK_RE,
                         xk_im => FFT_XK_IM,
                         xn_index => open,
                         xk_index => open,
                         rfd => open,
                         busy => open,
                         dv => open,
                         edone => open,
                         done => open);

end Behavioral;

4.floating point flag msg upon execution???

Dear group,
     I have this f77 program (huge) that runs on our SUN sparc machine
(OS 5.9). It will run and work normally, however, everytime you run it,
at the end of the execution, it will give you a NOTE, like the
following:

 Note: IEEE floating-point exception flags raised:
    Inexact;  Underflow;
 IEEE floating-point exception traps enabled:
    overflow;  division by zero;  invalid operation;
 Nonstandard floating-point mode enabled
 See the Numerical Computation Guide, ieee_flags(3M), ieee_handler(3M),
 ieee_sun(3M)

How do you get rid of it? or suppress it? I am running it in a batch
run fashion, so these print out kind of slow things down. Even after I
direct all the printout to /dev/null dump, it still print out the note
to the console, could anyone help?

Thanks a bunch!

5.Block-ram FIFO in Xilinx

Hello,
I have generated a block-ram based FIFO queue (2 independent clocks, 2
inputs, 1 output) with the use of Core Generator. In the creator I used the
36 bit data bus. Is it possible to parameterize this variable?
I think, that the Xilinx doesn't give such possibility. The generated code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifa IS
 port (
 din: IN std_logic_VECTOR(0 downto 0);
 rd_clk: IN std_logic;
 rd_en: IN std_logic;
 rst: IN std_logic;
 wr_clk: IN std_logic;
 wr_en: IN std_logic;
 dout: OUT std_logic_VECTOR(0 downto 0);
 empty: OUT std_logic;
 full: OUT std_logic);
END fifa;

ARCHITECTURE fifa_a OF fifa IS
-- synthesis translate_off
component wrapped_fifa
 port (
 din: IN std_logic_VECTOR(0 downto 0);
 rd_clk: IN std_logic;
 rd_en: IN std_logic;
 rst: IN std_logic;
 wr_clk: IN std_logic;
 wr_en: IN std_logic;
 dout: OUT std_logic_VECTOR(0 downto 0);
 empty: OUT std_logic;
 full: OUT std_logic);
end component;

-- Configuration specification
 for all : wrapped_fifa use entity
XilinxCoreLib.fifo_generator_v4_1(behavioral)
  generic map(
   c_has_int_clk => 0,
   c_rd_freq => 1,
   c_wr_response_latency => 1,
   c_has_srst => 0,
   c_has_rd_data_count => 0,
   c_din_width => 1,
   c_has_wr_data_count => 0,
   c_full_flags_rst_val => 1,
   c_implementation_type => 2,
   c_family => "virtex2p",
   c_use_embedded_reg => 0,
   c_has_wr_rst => 0,
   c_wr_freq => 1,
   c_underflow_low => 0,
   c_has_meminit_file => 0,
   c_has_overflow => 0,
   c_preload_latency => 1,
   c_dout_width => 1,
   c_rd_depth => 1024,
   c_default_value => "BlankString",
   c_mif_file_name => "BlankString",
   c_has_underflow => 0,
   c_has_rd_rst => 0,
   c_has_almost_full => 0,
   c_has_rst => 1,
   c_data_count_width => 10,
   c_has_wr_ack => 0,
   c_use_ecc => 0,
   c_wr_ack_low => 0,
   c_common_clock => 0,
   c_rd_pntr_width => 10,
   c_use_fwft_data_count => 0,
   c_has_almost_empty => 0,
   c_rd_data_count_width => 10,
   c_enable_rlocs => 0,
   c_wr_pntr_width => 10,
   c_overflow_low => 0,
   c_prog_empty_type => 0,
   c_optimization_mode => 0,
   c_wr_data_count_width => 10,
   c_preload_regs => 0,
   c_dout_rst_val => "0",
   c_has_data_count => 0,
   c_prog_full_thresh_negate_val => 1020,
   c_wr_depth => 1024,
   c_prog_empty_thresh_negate_val => 3,
   c_prog_empty_thresh_assert_val => 2,
   c_has_valid => 0,
   c_init_wr_pntr_val => 0,
   c_prog_full_thresh_assert_val => 1021,
   c_use_fifo16_flags => 0,
   c_has_backup => 0,
   c_valid_low => 0,
   c_prim_fifo_type => "1kx18",
   c_count_type => 0,
   c_prog_full_type => 0,
   c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifa
  port map (
   din => din,
   rd_clk => rd_clk,
   rd_en => rd_en,
   rst => rst,
   wr_clk => wr_clk,
   wr_en => wr_en,
   dout => dout,
   empty => empty,
   full => full);
-- synthesis translate_on

END fifa_a;

There are 2 parameters: c_din_width =>36  and c_dout_width => 36.  I can't
use here values greater than 36. What is the use of this parameters? Can I
change this parameters values to i.e. 20?
I would like to use the queue with different sizes of the data bus. Is it a
good solution to create a maximum size data bus and use it to write there
smaller data?
Or maybe it is better to create a 1bit queue, and with the use of GENERATE
command generate N 1 bit queues to have a N-bit queue?

Device is Virtex2Pro.

Regards,
zlotawy

6. FIFO full/empty

7. Error in FIFO Simulation ISE Xilinx

8. Xilinx Asynchronous FIFO