Using carry chain of counters for term count detect



  • 1. a new thread would be nice
    rickman wrote: > function sllint (x, sh : natural) return natural is > begin > return x*(2**sh); > end sllint; > I am not clear on what happens when I shift the value of Addr left by > 2 and significant bits extend beyond the defined range. The function, as written, will return x*(2**sh) up to the natural range. It knows nothing about any other range unless you add a parameter to to function. I would use numeric_std.unsigned and the shift_left function, and to_integer(my_uns, my_len) as needed. -- Mike Treseler
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  • 3. Assigning Values to Enumerated Types
    This seems simple, but I've been unable to find the answer. I have an enumerated type like this: type opmode_type is (m, p_plus_m, p_minus_m, m_plus_c...); signal opmode : opmode_type; As I understand it, the synthesizer will assign sequential values to these (i.e., m=1, p_plus_m=2). But I need to assign particular (3-bit signed) values to these: e.g., m="101", p_plus_m="110". Is there a way to do this? Perhaps I need to do something else entirely. I supposed I could use aliases to assign names to the constants. I could make a constant array and somehow index it (maybe with the enumerated type?). Or maybe I could make a record? type opmode_type is record m, p_plus_m, ... : unsigned(2 downto 0); signal opmode : opmode_type := ("101","110",...); and then access the opmode with a field, as in: opmode.p_plus_m I just wondered what is most stylistically proper way to do this. -Kevin
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    Quick question: is it possible to have a scenario where you can use an FPGA as a true bidirectional pipe without caring about the direction? I'm referring to problem below: entity true_bidir is port ( io_a : inout : std_logic; io_b : inout : std_logic ); end entity; architecture bidir_arch of true_bidir is begin io_a <= io_b; io_b <= io_a; end architecture; This will not map (not even through Synplicity), because I'm getting an error saying, hey, you need a buffer or register between these pins. So, is it possible with some kind of code trick to allow a true bidirectional pipe through an FPGA? I don't care about a direction. I would think, in theory, you could map a 'Z' to a 'Z' and thus not worry about a buffer. I'm using a Virtex 4. Thanks Ken XXXX@XXXXX.COM

Using carry chain of counters for term count detect

Postby rickman » Sun, 16 Aug 2009 07:36:40 GMT

I typically use down counters that are loaded with an initial value
and output a flag when reaching zero.  Sometimes the tools use the
carry chain and other times they don't.  I seem to recall that this
was discussed here a few months ago and someone posted a function or
other VHDL code that would produce a carry chain every time.  I
typically use a MOD operator for the counter, but the code I saw used
an integer for the count and subtracted one in the conditional of an
IF, then used the same expression in the counter assignment if the
result was not less than zero.  It appears that this was optimized to
share the same logic for both expressions.

I can't find this thread.  Anyone remember it and some keywords that
would let me find it?  There may be something wrong with Google
groups.  I search on "counter carry chain" and it finds *NO*


Re: Using carry chain of counters for term count detect

Postby KJ » Sun, 16 Aug 2009 10:17:29 GMT

> and output a flag when reaching zero. 

>> I can't find this thread. nyone remember it and some keywords that
>> would let me find it? here may be something wrong with Google
>> groups.  search on "counter carry chain" and it finds *NO*

I think this is the link you're looking for.  Andy's post from June 19
is the 8th one in the thread.

 http://www.**--****.com/ +counter+%22Andy%22+group:comp.lang.vhdl

Kevin Jennings

Re: Using carry chain of counters for term count detect

Postby rickman » Mon, 17 Aug 2009 12:13:51 GMT

I guess that is the one.  I don't see where they brought out the carry
flag to use elsewhere though and when I implement this, I get two
adders and the one generating the term count uses extra logic just to
get the carry out of the chain.  This is using the Lattice tools in
their XP parts.

I seem to recall making this work by adding an extra bit to the input
value and separating the msb of the output as the carry.  I'll give
that a try.


Re: Using carry chain of counters for term count detect

Postby Brian Davis » Mon, 17 Aug 2009 23:18:44 GMT

 Not specific to your down counter problem, but I posted a
snippet a few years back that showed operand padding to
pull out the carry/overflow:

 http://www.**--****.com/ #99517

I'd first seen that in another post years ago,
that I can't locate anymore...

 I've also noticed troubles with the google archive search,
I've been using the archive search on instead



Re: Using carry chain of counters for term count detect

Postby Andy » Tue, 18 Aug 2009 02:26:14 GMT

Wow, what's old is new again...

I should note that since then, I have noticed that while the RTL view
from Synplify indicates using the next bit (carry), the technology
view sometimes comes up with something better, not necessarily using
the carry chain the way one would expect.

That said, I have never seen it do worse than a "count = 0"

Also be aware that the "count - 1<< 0" (or "count + 1>> 2**n-1") trick
only works with integer types, not with unsigned vector types.


Re: Using carry chain of counters for term count detect

Postby JimLewis » Wed, 19 Aug 2009 01:15:48 GMT

Hi Rick,
Integers and such are great for sim run time, however, if you are not
getting the hardware you want, here is an array based algorithm that
only uses one carry cell to implement the zero detect.  It has a few
extras that you may want to remove.  BaseReg is the loadable base
register.  CntReg keeps the current count value.  IntReg is a
registered version of the zero detect.

SynthWorks VHDL training

TimerProc : process (Clk, nReset)
  variable Dec : unsigned(CntReg'Length downto 0) ;
  if (nReset = '0') then
    BaseReg <= (others => '0') ;
    CntReg  <= (others => '0') ;
    IntReg  <= '0' ;
  elsif rising_edge(Clk) then
    if (TimerSel = '1' and Read = '0') then
      BaseReg <= unsigned(DataIn) ;
    end if ;
    Dec  := ('0' & CntReg) - 1 ;
    if (Dec(Dec'Left) = '1') then
      CntReg  <= BaseReg ;
      CntReg  <= Dec(CntReg'Range);
    end if ;
    IntReg    <= Dec(Dec'Left) ;
  end if ;
end process ;

Re: Using carry chain of counters for term count detect

Postby Andy » Wed, 19 Aug 2009 03:12:56 GMT

That's about the cleanest example using vectors I've seen.

I'm not sure it wouldn't be subject to the same final optimizations
from Synplify (et al?), since those optimizations were related more to
the entire carry chain than to just the end of it. Although outputting
the carry bit in the IntReg register would likely give it a strong
nudge towards preserving the carry bit intact (if not the entire
chain). I've not checked any results from integer-coded
implementations that also registered (count - 1 < 0) as a boolean

Be careful if CntReg'Range is not "n downto 0".


Re: Using carry chain of counters for term count detect

Postby rickman » Wed, 19 Aug 2009 10:46:22 GMT

I don't have any problem getting the basic counter to use the carry
chain, but I can not get the carry out for other purposes.  The result
seems to depend on size and how the tool is invoked.  If I use the
Lattice tool, an 8 bit counter uses 3 LUTs to detect the terminal
count.  At 16 bits it duplicates the adder chain and pulls off the
carry out.  Using Synplify directly the technology view shows two
adders while the RTL view shows one adder with 24 bits.  The carry
comes out of the top and the lower N bits are used for the counter.
Go figure...


Similar Threads:

1.Counter with carry out at embedded bit.

Sorry is the subject sounds confusing, was the best description I
could come up with...

Below is the code I have some questions about..
What I want is a 10bit counter (which acts as a write address to a
ram) with a signal indicating the following counter transitions :
  and so forth for the rest of the 10bit values...
To do so, I've split up the counter in two halves as you can see in
the code.
Functionally, everything looks OK. The synthesiser makes two seperate
counters with the carry out of the first one, feeding the second. No
carry resource are used for that connection. But I'd like the
synthesiser (XST in my case) to use one long carry chain (one 10bit
counter) & make a connection at the right carry position to allow for
the signal. I took a closer look to the Virtex2pro slice architecture
& according to the datasheets, a connection like the one I want is

1. Can anyone give me any hints or so on how to code such a counter so
that the synthesis tool get my point in using one big counter ?
2. How could I make the whole thing parameterisable ? I have a
constant which indicates the cycle at wich the counter should output
the signal. Do I need to go for something like :
  constant c_carryposition : natural = log(c_cycle)/log(2)

Thanks for any replies..

library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL;																	 
entity Counter_with_signalling is
	Port (
		clk : in std_logic;		
		Cnt_ena, Rst : in std_logic;
		Count : out std_logic_vector(10 downto 0);
		RdRq : out std_logic
end Counter_with_signalling;

architecture Behavioral of Counter_with_signalling is

signal countL : std_logic_vector(4 downto 0);
signal countL_async : std_logic_vector(5 downto 0);
signal countH_async, countH : std_logic_vector(5 downto 0);


countL_async <= ('0' & countL) + 1;
countH_async <= countH + countL_async(5);

process (clk)
  if rising_edge(clk) then
    if Rst = '1' then
      countL <= (others => '0');
      countH <= (others => '0');
    else if Cnt_ena = '1' then
           countL <= countL_async(4 downto 0);
           countH <= countH + countL_async(5);
    end if;
  end if; 
  RdRq <= countL_async(5);
end if;
end process;

Count <= countH & countL;

end Behavioral;

2.Up/Down Binary Counter with Dynamic Count-to Flag

I need to simulate this thing in Verilog
hdl_lab/tema_pdf/DW03_bictr_dcnto.pdf :)

And here is my counter.v file

module counter(data, up_dn, cen, load, clk, count, tercnt, reset,
parameter width=4;

input[width-1:0] data;
input[width-1:0] count_to;
input up_dn, cen, load, clk, reset;

output [width-1:0] count;
reg [width-1:0] count;
output tercnt;
reg tercnt;

always @(posedge clk or negedge reset)
    if (~reset) begin
        else begin
                 if(~load) begin
                     else begin
                              if (cen) begin
                                             if (up_dn) begin
																					if (count==count_to)
                                                 else begin
																					if (count==count_to)

always @(count or up_dn)

			if (&count && up_dn)
								tercnt <= 1;

			if (~|count && !up_dn)
												tercnt <= 1;

						tercnt <= 0;



The problem is that when the count reaches to the count_to value(witch
is an input signal), tercn signal(terminate counting) dosent goes to

What do i do wrong?
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3.Count with specific bits of the counter

Hi all,

I am trying to create a counter of say 10 bits, where only some of
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So for example if that 10-bit control signal is 0000110011 then the
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My idea is a single bit ripple carry adder structure where multiplexers
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the right ones. I am looking for a more elegant VHDL-style description.
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I'm trying to get Synopsys Design Compiler to synthesize
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Merging Cascaded Adders With a Carry
If your design has two cascaded adders and one has a bit input, VHDL
Compiler replaces the two adders with a simple adder that has a carry
Example: z <= a + b + cin;

Now, "cin" can not be of type "bit", because bits can not be added,
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which is insane.

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity CADD is port(
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	B: in unsigned(23 downto 0);
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	R: out unsigned(23 downto 0));
architecture RTL of CADD is
	function caddf(A: unsigned(23 downto 0); B: unsigned(23 downto 0); C : std_ulogic) return unsigned is
		variable n : natural range 0 to 1;
		variable r : unsigned(23 downto 0);
		if C='0' then
			n := 0;
			n := 1;
		end if;
		r := A + B + n;
		return r;
	R <= caddf(A,B,C);

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