Using carry chain of counters for term count detect

Similar Threads:

1.Counter with carry out at embedded bit.

Sorry is the subject sounds confusing, was the best description I
could come up with...

Below is the code I have some questions about..
What I want is a 10bit counter (which acts as a write address to a
ram) with a signal indicating the following counter transitions :
  31-->32
  63-->64
  95-->96
  127-->128
  and so forth for the rest of the 10bit values...
To do so, I've split up the counter in two halves as you can see in
the code.
Functionally, everything looks OK. The synthesiser makes two seperate
counters with the carry out of the first one, feeding the second. No
carry resource are used for that connection. But I'd like the
synthesiser (XST in my case) to use one long carry chain (one 10bit
counter) & make a connection at the right carry position to allow for
the signal. I took a closer look to the Virtex2pro slice architecture
& according to the datasheets, a connection like the one I want is
possible.

1. Can anyone give me any hints or so on how to code such a counter so
that the synthesis tool get my point in using one big counter ?
2. How could I make the whole thing parameterisable ? I have a
constant which indicates the cycle at wich the counter should output
the signal. Do I need to go for something like :
  constant c_carryposition : natural = log(c_cycle)/log(2)


Thanks for any replies..

***************************
START CODE
***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;																	 
entity Counter_with_signalling is
	Port (
		clk : in std_logic;		
		Cnt_ena, Rst : in std_logic;
		Count : out std_logic_vector(10 downto 0);
		RdRq : out std_logic
	);
end Counter_with_signalling;

architecture Behavioral of Counter_with_signalling is

signal countL : std_logic_vector(4 downto 0);
signal countL_async : std_logic_vector(5 downto 0);
signal countH_async, countH : std_logic_vector(5 downto 0);

begin

countL_async <= ('0' & countL) + 1;
countH_async <= countH + countL_async(5);

process (clk)
begin
  if rising_edge(clk) then
    if Rst = '1' then
      countL <= (others => '0');
      countH <= (others => '0');
    else if Cnt_ena = '1' then
           countL <= countL_async(4 downto 0);
           countH <= countH + countL_async(5);
    end if;
  end if; 
  RdRq <= countL_async(5);
end if;
end process;

Count <= countH & countL;

end Behavioral;

2.Up/Down Binary Counter with Dynamic Count-to Flag

Hi,
I need to simulate this thing in Verilog vega.unitbv.ro/~nicula/asd/
hdl_lab/tema_pdf/DW03_bictr_dcnto.pdf :)

And here is my counter.v file

module counter(data, up_dn, cen, load, clk, count, tercnt, reset,
count_to);
parameter width=4;


input[width-1:0] data;
input[width-1:0] count_to;
input up_dn, cen, load, clk, reset;


output [width-1:0] count;
reg [width-1:0] count;
output tercnt;
reg tercnt;



always @(posedge clk or negedge reset)
    if (~reset) begin
                      count<={width{4'b0000}};
	         end
        else begin
                 if(~load) begin
                                  count<=data;
                                end
                     else begin
                              if (cen) begin
                                             if (up_dn) begin
                                                         count<=count
+1;
																					if (count==count_to)
																						tercnt<=1;
                                                             end
                                                 else begin
 
count<=count-1;
																					if (count==count_to)
																						tercnt<=1;
                                                        end
                                            end
                             end
                  end

always @(count or up_dn)

			if (&count && up_dn)
								tercnt <= 1;

				else
			if (~|count && !up_dn)
												tercnt <= 1;

					else
						tercnt <= 0;


endmodule


****************************************************************************************************************

The problem is that when the count reaches to the count_to value(witch
is an input signal), tercn signal(terminate counting) dosent goes to
"1"

What do i do wrong?
thank you

3.Count with specific bits of the counter

Hi all,

I am trying to create a counter of say 10 bits, where only some of
these bits are used in counting. These bits will be indicated by a
second 10bit signal.

So for example if that 10-bit control signal is 0000110011 then the
count would be

0000000000
0000000001
0000000010
0000000011
0000010000
0000010001
0000010010
   .
   .
   .
0000110011

My idea is a single bit ripple carry adder structure where multiplexers
are used to by-pass specific adders so that the carry is only fed to
the right ones. I am looking for a more elegant VHDL-style description.
I'd appreciate the help.

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5.Using carry-in adders with Synopsys

I'm trying to get Synopsys Design Compiler to synthesize
an adder where I can control the carry-in input. The manual
says:

>>>>
Merging Cascaded Adders With a Carry
If your design has two cascaded adders and one has a bit input, VHDL
Compiler replaces the two adders with a simple adder that has a carry
input. 
Example: z <= a + b + cin;
<<<<

Now, "cin" can not be of type "bit", because bits can not be added,
right? So I have tried using other types 
(natural range 0 to 1, unsigned(0 downto 0))
but I can't get it to work: Synopsys synthesizes always two adders
which is insane.

Does anyone know how to make it to synthesize only one adder
e.g. from the following code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CADD is port(
	A: in unsigned(23 downto 0);
	B: in unsigned(23 downto 0);
	C: in std_ulogic;
	R: out unsigned(23 downto 0));
end;
architecture RTL of CADD is
	function caddf(A: unsigned(23 downto 0); B: unsigned(23 downto 0); C : std_ulogic) return unsigned is
		variable n : natural range 0 to 1;
		variable r : unsigned(23 downto 0);
	begin
		if C='0' then
			n := 0;
		else
			n := 1;
		end if;
		r := A + B + n;
		return r;
	end;
begin
	R <= caddf(A,B,C);
end;

6. Using the carry flag in standard C

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