Computer architecture
-
- Topics
- Replies
- Views
- Last post
-
- How to set 'set up time' in a Quartus Tool for a PCI Device
by naveenk23 » Wed, 26 Nov 2003 19:27:28 GMT - 3 Replies
- 132 Views
- Last post by Nial Stewart
Fri, 28 Nov 2003 19:27:28 GMT
- How to set 'set up time' in a Quartus Tool for a PCI Device
-
- Loading from Compact Flash on ML310...
by Xesium » Fri, 29 Feb 2008 07:11:58 GMT - 2 Replies
- 8 Views
- Last post by Xesium
Mon, 03 Mar 2008 07:11:58 GMT
- Loading from Compact Flash on ML310...
-
- LUT design / Transmission gates or pass transistors?
by abbas » Mon, 02 Feb 2009 15:03:14 GMT - 9 Replies
- 1 Views
- Last post by glen herrmannsfeldt
Sun, 08 Feb 2009 15:03:14 GMT
- LUT design / Transmission gates or pass transistors?
-
- Population Count circuit
by acd » Thu, 20 Sep 2007 22:37:49 GMT - 9 Replies
- 75 Views
- Last post by comp.arch.fpga
Thu, 20 Sep 2007 22:37:49 GMT
- Population Count circuit
-
- DSP/FPGA/video board?
by Georgi Beloev » Sun, 29 Aug 2004 00:03:31 GMT - 5 Replies
- 15 Views
- Last post by Georgi Beloev
Sun, 29 Aug 2004 00:03:31 GMT
- DSP/FPGA/video board?
-
- generate systemACE file in EDK
by kurapati77 » Thu, 02 Jun 2005 01:48:41 GMT - 2 Replies
- 80 Views
- Last post by Ed McGettigan
Tue, 07 Jun 2005 01:48:41 GMT
- generate systemACE file in EDK
-
- Please suggest NON Volatile FPGA Devices
by asimlink » Fri, 25 Jun 2010 14:43:34 GMT - 1 Replies
- 17 Views
- Last post by asimlink
Fri, 02 Jul 2010 14:43:34 GMT
- Please suggest NON Volatile FPGA Devices
-
- ISE : Linux - coregen, compxlib errors
by ashwin » Thu, 10 May 2007 15:40:38 GMT - 2 Replies
- 114 Views
- Last post by Eric Smith
Sat, 19 May 2007 15:40:38 GMT
- ISE : Linux - coregen, compxlib errors
-
- problem with IO in EDK 8.1
by Mich » Sat, 08 Apr 2006 03:05:52 GMT - 6 Replies
- 89 Views
- Last post by Guru
Mon, 17 Apr 2006 03:05:52 GMT
- problem with IO in EDK 8.1
-
- What is a "full custom" design?
by Paul Marciano » Tue, 18 Oct 2005 23:51:31 GMT - 5 Replies
- 29 Views
- Last post by vssumesh
Thu, 27 Oct 2005 23:51:31 GMT
- What is a "full custom" design?
-
- XdmHelpers:662
by joel.weddick » Wed, 24 Jan 2007 18:09:44 GMT - 2 Replies
- 69 Views
- Last post by skyworld
Fri, 02 Feb 2007 18:09:44 GMT
- XdmHelpers:662
-
- ERROR:Map:11 - serdes_4b_1to7_wrapper symbol "rx0" - more than one RLOC_ORIGIN
by lijia21cn » Tue, 24 Feb 2009 07:49:13 GMT - 4 Replies
- 106 Views
- Last post by reganireland
Mon, 02 Mar 2009 07:49:13 GMT
- ERROR:Map:11 - serdes_4b_1to7_wrapper symbol "rx0" - more than one RLOC_ORIGIN
-
- GF(233) example
by Weng Tianxiang » Sat, 05 Sep 2009 04:25:20 GMT - 6 Replies
- 99 Views
- Last post by Weng Tianxiang
Wed, 09 Sep 2009 04:25:20 GMT
- GF(233) example
-
- Tristate problem
by varin.vahia » Sun, 06 Mar 2005 16:01:31 GMT - 1 Replies
- 136 Views
- Last post by varin.vahia
Sat, 12 Mar 2005 16:01:31 GMT
- Tristate problem
-
- Writing IP-Cores while sleeping ;)
by Antti Lukats » Sun, 13 Feb 2005 06:58:32 GMT - 16 Replies
- 141 Views
- Last post by Eric Smith
Mon, 14 Feb 2005 06:58:32 GMT
- Writing IP-Cores while sleeping ;)
-
- Xilinx ML310 board's IO
by Wing Fong Wong » Sat, 05 Mar 2005 17:08:13 GMT - 3 Replies
- 12 Views
- Last post by Wing Fong Wong
Sat, 12 Mar 2005 17:08:13 GMT
- Xilinx ML310 board's IO
-
- get net name after place and route, ISE
by Matthew E Rosenthal » Fri, 13 Aug 2004 09:04:26 GMT - 1 Replies
- 104 Views
- Last post by Matthew E Rosenthal
Sun, 22 Aug 2004 09:04:26 GMT
- get net name after place and route, ISE
-
- Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
by Jonathan Bromley » Mon, 31 Aug 2009 05:07:38 GMT - 1 Replies
- 9 Views
- Last post by Jonathan Bromley
Fri, 04 Sep 2009 05:07:38 GMT
- Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
-
- Timing Diagram software recommendations?
by Nial Stewart » Sat, 25 Mar 2006 06:50:55 GMT - 2 Replies
- 36 Views
- Last post by Bob Perlman
Fri, 31 Mar 2006 06:50:55 GMT
- Timing Diagram software recommendations?
-
- Spartan IIE daisy chain problems
by Jerker Hammarberg (DST) » Sun, 14 Dec 2003 03:13:27 GMT - 2 Replies
- 77 Views
- Last post by Marc Baker
Tue, 16 Dec 2003 03:13:27 GMT
- Spartan IIE daisy chain problems
-
- Spartan-3: 5V -> 2.5V level shifting
by jidan1 » Fri, 15 Sep 2006 18:03:08 GMT - 17 Replies
- 56 Views
- Last post by jidan1
Thu, 21 Sep 2006 18:03:08 GMT
- Spartan-3: 5V -> 2.5V level shifting
-
- Cheating at homework (from " FPGA - software or hardware?"t
by JJ » Wed, 22 Feb 2006 01:04:38 GMT - 2 Replies
- 126 Views
- Last post by Chris Gammell
Thu, 23 Feb 2006 01:04:38 GMT
- Cheating at homework (from " FPGA - software or hardware?"t
-
- SD Card and FPGA
by Martin Schoeberl » Fri, 25 Feb 2005 03:25:28 GMT - 8 Replies
- 2 Views
- Last post by Antti Lukats
Sun, 27 Feb 2005 03:25:28 GMT
- SD Card and FPGA
-
- Interface on board ADC to Spartan 3E startkit
by krunal » Tue, 19 Feb 2008 15:47:41 GMT - 2 Replies
- 26 Views
- Last post by Frank Buss
Mon, 25 Feb 2008 15:47:41 GMT
- Interface on board ADC to Spartan 3E startkit
-
- use of memory in verilog(uegent please)
by ravindra28d » Sat, 13 Aug 2005 01:16:16 GMT - 1 Replies
- 68 Views
- Last post by ravindra28d
Tue, 16 Aug 2005 01:16:16 GMT
- use of memory in verilog(uegent please)
-
- Virtex-4 readback via ICAP
by Brac » Fri, 07 Apr 2006 00:51:46 GMT - 6 Replies
- 35 Views
- Last post by Austin Lesea
Wed, 12 Apr 2006 00:51:46 GMT
- Virtex-4 readback via ICAP
-
- ICMP checksum
by life.is.best » Sat, 15 Mar 2008 16:23:44 GMT - 1 Replies
- 18 Views
- Last post by life.is.best
Tue, 18 Mar 2008 16:23:44 GMT
- ICMP checksum
-
- PicoBlaze Assembler in C (was Assembler for PicoBlaze in Perl)
by Stephen Williams » Wed, 27 Oct 2004 00:37:33 GMT - 1 Replies
- 67 Views
- Last post by Stephen Williams
Fri, 29 Oct 2004 00:37:33 GMT
- PicoBlaze Assembler in C (was Assembler for PicoBlaze in Perl)
-
- timing constraint is impossible to meet
by Wojciech Zabolotny » Tue, 27 May 2008 23:31:27 GMT - 10 Replies
- 5 Views
- Last post by Gabor
Sun, 01 Jun 2008 23:31:27 GMT
- timing constraint is impossible to meet
-
- Vritex2PRO: LVDCI for inputs?
by austin » Sat, 10 May 2008 23:57:01 GMT - 1 Replies
- 128 Views
- Last post by austin
Sun, 18 May 2008 23:57:01 GMT
- Vritex2PRO: LVDCI for inputs?
-
- Counter ?
by » Sat, 21 Jul 2007 23:22:46 GMT - 33 Replies
- 2 Views
- Last post by Ralf Hildebrandt
Mon, 23 Jul 2007 23:22:46 GMT
- Counter ?
-
- query in a design
by kumar » Sun, 19 Nov 2006 11:56:23 GMT - 2 Replies
- 115 Views
- Last post by kumar
Sun, 19 Nov 2006 11:56:23 GMT
- query in a design
-
- ISE question on whats a "X_LUT3"?
by Fred » Thu, 01 Dec 2005 02:26:48 GMT - 3 Replies
- 144 Views
- Last post by Fred
Mon, 05 Dec 2005 02:26:48 GMT
- ISE question on whats a "X_LUT3"?
-
- "Implement Design" Error on ISE 6.3 webpack
by gallen » Thu, 28 Apr 2005 05:24:29 GMT - 2 Replies
- 19 Views
- Last post by Gabor
Mon, 02 May 2005 05:24:29 GMT
- "Implement Design" Error on ISE 6.3 webpack
-
- process trouble, error: multi source
by Benjamin Menk » Wed, 13 Apr 2005 08:21:05 GMT - 3 Replies
- 123 Views
- Last post by Jeremy Stringer
Thu, 21 Apr 2005 08:21:05 GMT
- process trouble, error: multi source
-
- microblaze with FSL
by upforever » Fri, 17 Feb 2006 11:33:43 GMT - 3 Replies
- 127 Views
- Last post by upforever
Sun, 19 Feb 2006 11:33:43 GMT
- microblaze with FSL
Who is online
Users browsing this forum: No registered users and 58 guest
Forum permissions
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum