Computer architecture
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- ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
by MM » Sun, 17 Oct 2010 00:08:19 GMT - 10 Replies
- 78 Views
- Last post by MM
Mon, 25 Oct 2010 00:08:19 GMT
- ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
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- Transfer data from one clock domain to another clock created by the same PLL/DCM
by Mike Treseler » Fri, 07 Jan 2011 05:18:13 GMT - 2 Replies
- 58 Views
- Last post by Mike Treseler
Sat, 15 Jan 2011 05:18:13 GMT
- Transfer data from one clock domain to another clock created by the same PLL/DCM
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- Using LVPECL_25 inputs in Spartan3e problem
by Giorgos_P » Thu, 28 Oct 2010 02:49:58 GMT - 6 Replies
- 77 Views
- Last post by John Adair
Thu, 04 Nov 2010 02:49:58 GMT
- Using LVPECL_25 inputs in Spartan3e problem
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- Reference book on Pci-express (Hardware and software point of view)
by Benjamin Couillard » Tue, 12 Apr 2011 16:30:21 GMT - 4 Replies
- 91 Views
- Last post by shyam
Mon, 18 Apr 2011 16:30:21 GMT
- Reference book on Pci-express (Hardware and software point of view)
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- Xilinx EasyPath Pricing
by muhammad_umer » Fri, 06 Aug 2010 22:41:29 GMT - 7 Replies
- 143 Views
- Last post by Jeff Cunningham
Mon, 09 Aug 2010 22:41:29 GMT
- Xilinx EasyPath Pricing
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- Trivia: Where are you on the HDL Map?
by Tim Wescott » Sun, 13 Feb 2011 07:25:46 GMT - 32 Replies
- 60 Views
- Last post by Jon Elson
Sun, 13 Feb 2011 07:25:46 GMT
- Trivia: Where are you on the HDL Map?
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- Actel Designer: how to compile VHDL top & EDIF submodule together?
by robotron » Mon, 17 Jan 2011 05:26:33 GMT - 5 Replies
- 97 Views
- Last post by Kryvor
Mon, 24 Jan 2011 05:26:33 GMT
- Actel Designer: how to compile VHDL top & EDIF submodule together?
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- Why is the Cyclone IV so expensive?
by Philipp Klaus Krause » Wed, 09 Feb 2011 01:23:37 GMT - 8 Replies
- 122 Views
- Last post by John Adair
Fri, 11 Feb 2011 01:23:37 GMT
- Why is the Cyclone IV so expensive?
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- How keep OPEN single bit in ucf
by c4cheema » Thu, 21 Oct 2010 03:29:34 GMT - 1 Replies
- 32 Views
- Last post by c4cheema
Sat, 23 Oct 2010 03:29:34 GMT
- How keep OPEN single bit in ucf
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- Cant launch ModelSim from Xilin ISE 12.1
by muhammad_umer » Wed, 22 Sep 2010 17:01:44 GMT - 2 Replies
- 4 Views
- Last post by HT-Lab
Fri, 01 Oct 2010 17:01:44 GMT
- Cant launch ModelSim from Xilin ISE 12.1
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- Concurrent Logic Timing
by rickman » Sat, 11 Dec 2010 11:51:55 GMT - 18 Replies
- 20 Views
- Last post by rickman
Thu, 16 Dec 2010 11:51:55 GMT
- Concurrent Logic Timing
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- DEADLINE EXTENDED - 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011)
by Khaled » Sun, 16 Jan 2011 18:57:04 GMT - 1 Replies
- 39 Views
- Last post by Khaled
Thu, 20 Jan 2011 18:57:04 GMT
- DEADLINE EXTENDED - 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011)
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- TCP Client using lwIP API
by micro » Tue, 24 Aug 2010 17:43:55 GMT - 2 Replies
- 45 Views
- Last post by Marc Jet
Sun, 29 Aug 2010 17:43:55 GMT
- TCP Client using lwIP API
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- NibzX7 processor
by jacko » Sat, 23 Apr 2011 15:22:45 GMT - 20 Replies
- 19 Views
- Last post by Jan Coombs
Wed, 27 Apr 2011 15:22:45 GMT
- NibzX7 processor
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- I Give Up!
by rickman » Sun, 23 Jan 2011 09:31:27 GMT - 23 Replies
- 50 Views
- Last post by Frank GOENNINGER
Sun, 23 Jan 2011 09:31:27 GMT
- I Give Up!
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- StratixII GX development board
by axalay » Thu, 07 Oct 2010 23:00:42 GMT - 1 Replies
- 37 Views
- Last post by axalay
Thu, 14 Oct 2010 23:00:42 GMT
- StratixII GX development board
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- IO pin question
by fasf » Fri, 22 Oct 2010 22:26:41 GMT - 13 Replies
- 67 Views
- Last post by Gabor
Fri, 29 Oct 2010 22:26:41 GMT
- IO pin question
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- Problems with Xilinx SDK and LwIP
by DaMunky89 » Sat, 19 Mar 2011 10:36:25 GMT - 6 Replies
- 72 Views
- Last post by DaMunky89
Sat, 26 Mar 2011 10:36:25 GMT
- Problems with Xilinx SDK and LwIP
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- Xilinx XST and a State Machine - A Mystery
by Darol Klawetter » Thu, 30 Sep 2010 01:00:45 GMT - 35 Replies
- 24 Views
- Last post by Andy
Sat, 09 Oct 2010 01:00:45 GMT
- Xilinx XST and a State Machine - A Mystery
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- INIT_B stays low
by salimbaba » Thu, 11 Nov 2010 16:52:50 GMT - 2 Replies
- 60 Views
- Last post by John Adair
Thu, 11 Nov 2010 16:52:50 GMT
- INIT_B stays low
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- Interconnection of multiple cores
by sebas » Thu, 09 Dec 2010 00:32:03 GMT - 6 Replies
- 63 Views
- Last post by RCIngham
Sun, 12 Dec 2010 00:32:03 GMT
- Interconnection of multiple cores
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- Strange issue wih a very simple VHDL code and Spartan 3A Starter kit board
by Francesco Da Riva » Tue, 11 Jan 2011 22:48:31 GMT - 8 Replies
- 34 Views
- Last post by Francesco Da Riva
Sat, 15 Jan 2011 22:48:31 GMT
- Strange issue wih a very simple VHDL code and Spartan 3A Starter kit board
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- SPF+ useable signalling range
by Roger » Fri, 09 Jul 2010 06:27:32 GMT - 3 Replies
- 24 Views
- Last post by Roger
Tue, 13 Jul 2010 06:27:32 GMT
- SPF+ useable signalling range
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- Job Vacancy at Imperial College
by gac1@ic.ac.uk » Sat, 02 Oct 2010 17:22:23 GMT - 1 Replies
- 83 Views
- Last post by gac1@ic.ac.uk
Tue, 05 Oct 2010 17:22:23 GMT
- Job Vacancy at Imperial College
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- First ICTP Regional Microelectronics Course on VHDL for Hardware Synthesis and FPGA Design in South and Southeast Asia
by andres » Sat, 02 Oct 2010 18:32:24 GMT - 1 Replies
- 99 Views
- Last post by andres
Wed, 06 Oct 2010 18:32:24 GMT
- First ICTP Regional Microelectronics Course on VHDL for Hardware Synthesis and FPGA Design in South and Southeast Asia
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- SPI ROM use for holding bitstreams
by Patrick » Sat, 02 Oct 2010 09:08:49 GMT - 1 Replies
- 27 Views
- Last post by Patrick
Sat, 09 Oct 2010 09:08:49 GMT
- SPI ROM use for holding bitstreams
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- ping pong buffer overflow issue
by salimbaba » Thu, 17 Mar 2011 18:26:42 GMT - 7 Replies
- 49 Views
- Last post by maxascent
Mon, 21 Mar 2011 18:26:42 GMT
- ping pong buffer overflow issue
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- ML505 NOT RECOGNIZED BY THE PC THROUGH PCI EXPRESS
by ouadrani » Sat, 16 Apr 2011 23:35:33 GMT - 3 Replies
- 138 Views
- Last post by maxascent
Sun, 24 Apr 2011 23:35:33 GMT
- ML505 NOT RECOGNIZED BY THE PC THROUGH PCI EXPRESS
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- CE compliance testing
by Fredxx » Mon, 23 Aug 2010 17:19:02 GMT - 25 Replies
- 8 Views
- Last post by Michael Schwingen
Thu, 26 Aug 2010 17:19:02 GMT
- CE compliance testing
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- Is Tier Logic doomed ? :-/
by whygee » Sun, 25 Jul 2010 21:28:46 GMT - 2 Replies
- 73 Views
- Last post by General Schvantzkoph
Wed, 28 Jul 2010 21:28:46 GMT
- Is Tier Logic doomed ? :-/
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- Spartan3 bidirectional 3.3V 5V level shifter
by rickman » Fri, 19 Nov 2010 02:11:40 GMT - 13 Replies
- 15 Views
- Last post by Sink0
Wed, 24 Nov 2010 02:11:40 GMT
- Spartan3 bidirectional 3.3V 5V level shifter
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