Computer architecture
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- ACTEL 8051s core
by Biswarup » Fri, 05 Jun 2009 23:41:30 GMT - 2 Replies
- 40 Views
- Last post by Antti.Lukats@googlemail.com
Wed, 10 Jun 2009 23:41:30 GMT
- ACTEL 8051s core
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- RS-232 Bus controller design in VHDL
by ikki » Wed, 12 Nov 2008 03:59:05 GMT - 20 Replies
- 6 Views
- Last post by Mike Treseler
Tue, 18 Nov 2008 03:59:05 GMT
- RS-232 Bus controller design in VHDL
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- Read/Write SRAM on Spartan3 Starter kit
by Nick » Thu, 17 Jan 2008 20:02:28 GMT - 4 Replies
- 98 Views
- Last post by Nick
Sun, 20 Jan 2008 20:02:28 GMT
- Read/Write SRAM on Spartan3 Starter kit
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- SOLVED: How to generate STAPL with "pulse PROG" in Impact?
by Wojciech Zabolotny » Fri, 23 Mar 2007 00:32:47 GMT - 1 Replies
- 133 Views
- Last post by Wojciech Zabolotny
Mon, 26 Mar 2007 00:32:47 GMT
- SOLVED: How to generate STAPL with "pulse PROG" in Impact?
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- System Generator Error
by anilcelebi » Tue, 01 Apr 2008 00:45:48 GMT - 1 Replies
- 127 Views
- Last post by anilcelebi
Tue, 08 Apr 2008 00:45:48 GMT
- System Generator Error
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- Tcl used in Modelsim?
by Davy » Sun, 23 Apr 2006 18:34:50 GMT - 2 Replies
- 41 Views
- Last post by Hans
Mon, 24 Apr 2006 18:34:50 GMT
- Tcl used in Modelsim?
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- Ed Hardy man jeans
by brandjean12 » Sat, 21 Mar 2009 11:30:54 GMT - 1 Replies
- 92 Views
- Last post by brandjean12
Mon, 23 Mar 2009 11:30:54 GMT
- Ed Hardy man jeans
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- Infiniband
by brucewillis » Sun, 15 Aug 2004 00:18:19 GMT - 2 Replies
- 46 Views
- Last post by Sylvain Munaut
Sat, 21 Aug 2004 00:18:19 GMT
- Infiniband
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- virtex II pro - own core on plb with 2 interrupts
by SvenA » Sun, 09 Dec 2007 07:29:41 GMT - 2 Replies
- 14 Views
- Last post by Matthew Hicks
Tue, 18 Dec 2007 07:29:41 GMT
- virtex II pro - own core on plb with 2 interrupts
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- PAL problems (again)
by drwho8__NOTME__ » Thu, 07 Apr 2005 04:26:30 GMT - 8 Replies
- 119 Views
- Last post by Paul Urbanus
Mon, 11 Apr 2005 04:26:30 GMT
- PAL problems (again)
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- LUT 4:1 VS FF
by Claudio » Sat, 15 Oct 2005 02:44:29 GMT - 8 Replies
- 132 Views
- Last post by Peter Alfke
Mon, 17 Oct 2005 02:44:29 GMT
- LUT 4:1 VS FF
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- Xilinx AREA_GROUP constraint and relative placement
by MM » Sun, 05 Apr 2009 07:08:40 GMT - 1 Replies
- 133 Views
- Last post by MM
Wed, 08 Apr 2009 07:08:40 GMT
- Xilinx AREA_GROUP constraint and relative placement
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- Chipscope and debugger through the same JTAG port
by MM » Wed, 01 Nov 2006 06:15:22 GMT - 5 Replies
- 51 Views
- Last post by MM
Tue, 07 Nov 2006 06:15:22 GMT
- Chipscope and debugger through the same JTAG port
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- Xilinx ML300 JTAG Configuration Problem
by antti » Thu, 03 Jul 2003 10:12:31 GMT - 2 Replies
- 29 Views
- Last post by Peter Ryser
Sat, 12 Jul 2003 10:12:31 GMT
- Xilinx ML300 JTAG Configuration Problem
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- Quantitive value for slew rate
by axr0284 » Wed, 25 Feb 2009 06:49:46 GMT - 1 Replies
- 98 Views
- Last post by axr0284
Sat, 28 Feb 2009 06:49:46 GMT
- Quantitive value for slew rate
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- A Very good VLSI Chip design website
by chipdesignart » Thu, 08 Mar 2007 20:30:04 GMT - 3 Replies
- 4 Views
- Last post by Francesco
Mon, 12 Mar 2007 20:30:04 GMT
- A Very good VLSI Chip design website
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- Dual-port and single-port BlockRAM instantiation
by arkagaz » Wed, 10 Dec 2003 17:30:39 GMT - 6 Replies
- 136 Views
- Last post by arkagaz
Tue, 16 Dec 2003 17:30:39 GMT
- Dual-port and single-port BlockRAM instantiation
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- 50+ pages fresh from Antti's brain
by Antti » Fri, 06 Nov 2009 03:28:07 GMT - 14 Replies
- 91 Views
- Last post by nico
Thu, 12 Nov 2009 03:28:07 GMT
- 50+ pages fresh from Antti's brain
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- V5LXT support for ISE released yesterday
by Antti » Fri, 27 Oct 2006 18:31:07 GMT - 3 Replies
- 21 Views
- Last post by Antti
Thu, 02 Nov 2006 18:31:07 GMT
- V5LXT support for ISE released yesterday
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- Timing model for MultiTrack interconnects in Stratix?
by petersommerfeld » Thu, 29 Jan 2004 13:37:46 GMT - 4 Replies
- 137 Views
- Last post by Paul Leventis (at home)
Sat, 31 Jan 2004 13:37:46 GMT
- Timing model for MultiTrack interconnects in Stratix?
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- Bus Macros
by praetorian » Wed, 20 Jul 2005 02:02:25 GMT - 6 Replies
- 82 Views
- Last post by praetorian
Wed, 27 Jul 2005 02:02:25 GMT
- Bus Macros
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- Burn to an internal prom Spartan-3an
by izaak » Tue, 08 Jun 2010 22:49:01 GMT - 2 Replies
- 113 Views
- Last post by Gabor
Wed, 16 Jun 2010 22:49:01 GMT
- Burn to an internal prom Spartan-3an
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- adding real UART to xilinx ultracontroller design.
by Matthew E Rosenthal » Fri, 06 Aug 2004 02:06:07 GMT - 7 Replies
- 112 Views
- Last post by Shalin Sheth
Sun, 08 Aug 2004 02:06:07 GMT
- adding real UART to xilinx ultracontroller design.
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- Xilinx DDR2 Interface
by ben » Wed, 23 Apr 2008 09:01:45 GMT - 7 Replies
- 41 Views
- Last post by ben
Tue, 29 Apr 2008 09:01:45 GMT
- Xilinx DDR2 Interface
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- PCI-X DMA problem w/ Xeon?
by Mark Schellhorn » Tue, 06 Jul 2004 23:38:26 GMT - 3 Replies
- 87 Views
- Last post by Matthias Mler
Tue, 13 Jul 2004 23:38:26 GMT
- PCI-X DMA problem w/ Xeon?
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- Problem for CNA/CAN conversion
by alexandre.abellard » Wed, 07 Apr 2004 16:16:37 GMT - 2 Replies
- 2 Views
- Last post by Nicolas Matringe
Wed, 14 Apr 2004 16:16:37 GMT
- Problem for CNA/CAN conversion
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- Removing set/reset logic for shift register (HDL ADVISOR )
by david.lamb » Fri, 08 Oct 2004 11:27:06 GMT - 11 Replies
- 99 Views
- Last post by Ray Andraka
Sun, 17 Oct 2004 11:27:06 GMT
- Removing set/reset logic for shift register (HDL ADVISOR )
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- Missing ISE HTML online help (pdf sucks!)
by Morten Leikvoll » Sun, 02 Jul 2006 00:58:22 GMT - 2 Replies
- 54 Views
- Last post by pbdelete
Thu, 06 Jul 2006 00:58:22 GMT
- Missing ISE HTML online help (pdf sucks!)
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- Wanted Actel ProAsic RAM VHDL models
by scd » Fri, 15 Jul 2005 16:29:09 GMT - 2 Replies
- 12 Views
- Last post by Hans
Sun, 17 Jul 2005 16:29:09 GMT
- Wanted Actel ProAsic RAM VHDL models
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- Partial Reconfiguration using XUPV2P
by David » Fri, 13 Oct 2006 21:51:54 GMT - 1 Replies
- 142 Views
- Last post by David
Sun, 15 Oct 2006 21:51:54 GMT
- Partial Reconfiguration using XUPV2P
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- ADC08D1500 + Virtex-4
by Vivek Menon » Sat, 15 Jul 2006 03:21:32 GMT - 1 Replies
- 90 Views
- Last post by Vivek Menon
Thu, 20 Jul 2006 03:21:32 GMT
- ADC08D1500 + Virtex-4
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- xilinx software licenses and updates
by E.S. » Wed, 10 Nov 2004 02:32:02 GMT - 1 Replies
- 34 Views
- Last post by E.S.
Fri, 19 Nov 2004 02:32:02 GMT
- xilinx software licenses and updates
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- Synopsys Designware IP... can be used for Xilinx FPGA??
by mr.cromr » Tue, 07 Jun 2005 01:58:57 GMT - 6 Replies
- 100 Views
- Last post by Ken McElvain
Tue, 07 Jun 2005 01:58:57 GMT
- Synopsys Designware IP... can be used for Xilinx FPGA??
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- V4FX60, hard temac, MPMC2 and SoDIMM
by morphiend » Wed, 20 Jun 2007 01:03:25 GMT - 2 Replies
- 28 Views
- Last post by MM
Thu, 28 Jun 2007 01:03:25 GMT
- V4FX60, hard temac, MPMC2 and SoDIMM
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- Is Altera Cyclone a good choice ?
by alessandro.strazzero » Thu, 03 Mar 2005 21:37:08 GMT - 14 Replies
- 13 Views
- Last post by Petter Gustad
Sun, 06 Mar 2005 21:37:08 GMT
- Is Altera Cyclone a good choice ?
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- dual clock fifo
by FPGA » Thu, 27 Mar 2008 07:28:50 GMT - 23 Replies
- 9 Views
- Last post by nico
Sat, 05 Apr 2008 07:28:50 GMT
- dual clock fifo
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